(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of tungsten plug metallization in the manufacture of integrated circuits.
(2) Description of the Prior Art
Tungsten-plug metallization is widely used in the art for vertical interconnects of various metal layers in integrated circuit fabrication. A conventional tungsten chemical vapor deposition (W-CVD) process is illustrated in FIG. 1. A contact hole is opened in a dielectric layer 14 overlying a semiconductor substrate 10. A glue layer 18 is deposited over the dielectric layer and within the contact opening. Typically, the glue layer, which is used as a nucleation layer for the CVD tungsten, comprises titanium nitride, 500 to 1500 Angstroms in thickness, with a thin titanium underlayer, 100 to 500 Angstroms, for adhesion. A tungsten layer 22 is then deposited by CVD and etched back, as shown in FIG. 2, to form the tungsten plug. However, this process if associated with high complexity and cost, high via resistance, and poor controllability of particulation. Moreover, the continuous scaling down of the contact hole size causes great difficulty in filling the contact hole.
U.S. Pat. No. 5,286,675 to Chen et al teaches a procedure for forming tungsten plugs including the conventional Ti/TiN as the glue layer and the use of reactive ion etching (RIE) to remove the tungsten layer to form the plug. U.S. Pat. No. 5,397,742 to Kim shows the use of a TiSi.sub.2 glue layer overlying a Ti/TiN layer which is etched away after the tungsten plug is formed in order to remove tungsten residue.